Data processing systems utilize fixed point arithmetic logic units (ALUs) for making fixed point, or floating point, arithmetic calculations. Such systems sometimes utilize separate floating point arithmetic calculation units, i.e., units used only for making floating point arithmetic calculations. Usually fixed point arithmetic logic units are arranged to provide integral operation with, i.e., as integrally functioning parts of, the central processing unit, the CPU having essentially direct access to the ALU via internal logic and busses requiring no intermediate interface units for such purpose. Floating point computation units, however, are often formed as entities which are separate from the CPU and require suitable interface logic to permit communication therebetween so that the CPU can use the floating point unit for making the desired floating point calculations. The interface logic must handle the various control signals and data transfers that are necessary in order to control the FPU calculations, as well as to provide the input data to, and the calculated output from, the FPU.
Further, it is usually desirable that such floating point units be permitted to operate in parallel with the operation of the CPU, since the overlapping of activities will increase the overall system performance. Moreover, in asynchronously operated systems the FPU can be arranged to operate at a different operating speed from the speed of operation of the CPU, i.e. such units operate on different internal clock systems. Because of such asynchronous operation, suitable control signals must be devised for coordinating the operation of the FPU with that of the CPU both in the starting of its calculation operations and in the transfer of data in both directions between the units.